One of the most important recent developments in semiconductors, both from the point of view of physics and for the purpose of device developments, has been the achievement of structures in which the electronic behavior is essentially two-dimensional (2D). This means that, at least for some phases of operation of the device, the carriers are confined in a potential such that their motion in one direction is restricted and thus is quantized, leaving only a two-dimensional momentum which characterizes motion in a plane normal to the confining potential. The major systems where such 2D behavior has been studied are MOS and HEMT structures, quantum wells and superlattices. More recently, quantization has been achieved in 1-dimension through the formation of quantum wires and in zero” dimensions through the use of quantum dots.
In the past 30 years there has been considerable research involving 2D electronic gases (2DEGs) and 2D hole gases (2DHGs), and much continues to this day. 2DEGs due to their presence in transistor like structures formed from semiconductors have offered researchers a mature system for providing extremely high mobility electrons, especially at low temperatures. When cooled to 4K, 2DEGs may have mobilities of the order of 1,000,000 cm2/Vs and even lower temperatures can lead to further increases in mobility. Specially grown, state of the art heterostructures with mobilities around 30,000,000 cm2/Vs have been made, see for example A. Kumar et al in “Non-Conventional Odd-Denominator Fractional Quantum Hall States in the Second Landau Level” (Phys. Rev. Lett., Vol. 105, 246808, 2010). These enormous mobilities have provided a test bed for exploring fundamental physics, such as for example the first demonstration of the integer and fractional quantum Hall effects, since besides confinement and effective mass, the electrons do not interact with the semiconductor very often. For reference mobilities in 2DHG systems are smaller than those of most 2DEG systems, in part due to larger effective masses of holes, such that a few 1,000 cm2/Vs are already considered high mobility.
Electrical conductivity is proportional to the product of mobility and carrier concentration and accordingly the same conductivity can come from a small number of electrons with high mobility for each, or a large number of electrons with a small mobility for each. For metals, it would not typically matter which of these is the case, since most metal electrical behavior depends on conductivity alone. Therefore, mobility is relatively unimportant in metal physics. On the other hand, for semiconductors, the behavior of transistors and other devices can be very different depending on whether there are many electrons with low mobility or few electrons with high mobility and accordingly, mobility is a very important parameter for semiconductor materials where almost always, higher mobility leads to better device performance, with other things equal. As within a semiconductor device the same electrical conductivity can be derived from a small device geometry with a low number of high mobility electrons and a large device geometry with a large number of low mobility electrons. Accordingly, 2DEGs allow for smaller device geometries and faster devices.
At the same time the realization of the split gate opened up the possibility to observe several new quantum effects in electron transport generating a field of research on its own. Amongst split gates is the quantum point contact (QPC), whereby a narrow constriction with a tunable width comparable to the Fermi wavelength is fabricated on a 2DEG. The QPC led to the observation of one-dimensional ballistic transport, a regime where the conductance is quantized in even steps of 2 e2/h as a function of the constriction width. QPCs have not only allowed research into ballistic quantum transport and mesoscopic physics but today very similar fabrication techniques are employed to fabricate devices for studying electronic transport in quantum dots, electron interferometers, and phase-coherent mesoscopic circuits.
Further, when the electron mobility within a 2DEG exceeds ˜105 cm2/V·s additional quantum effects can arise within a magnetic field, such as the Fractional Quantum Hall (FQH) effect. This counter-intuitive phenomenon involves the two-dimensional system acquiring fractional effective charges, quantum statistics and quantum numbers, all driven by electron-electron interactions. This is in stark contrast with the Integer Quantum Hall (IQH) effect whose emergence does not involve any interactions and consequently is much more robust against disorder.
Whilst detrimental to the electronic mobility of its 2DEG, split gates fabricated on high-mobility GaAs/AlGaAs heterostructures have led to important insights. For instance, shot noise measurements were used to determine effective charges in FQH circuits, electron interferometry with FQH quasiparticles is now performed in Fabry-Perot, and/or Mach-Zehnder interferometers which are electronic equivalent to those used in optics.
However, a significantly limitation is the processing required to fabricate these gates, which results in unwanted degradation of the electron mobility. This is particularly damaging for delicate many-body quantum states such as the 5/2 and 12/5 FQH states. These states are unusual in that their quantum statistics is believed to emanate from a non-Abelian lineage, but unfortunately their small energy many-body gaps of ˜500 mK and ˜50 mK respectively are affected by disorder of any kind. As such, it has been difficult thus far to study these states in gated structures to date except for a limited number of tour de force experiments performed on the 5/2 FQH state.
Within the prior art the approaches to fabricating a “gated device” with a high-mobility 2DEG, such as those found in MOSFETs, HEMTs, etc. exploit direct lithography, be it photolithography or e-beam lithography, directly on the high-quality wafer where the 2DEG is to be formed. However, these techniques lead to rapid degradation of the 2DEG quality during processing which then can limits the mobility of the electronic devices. Accordingly, it would be beneficial to provide a process/technique which circumvents this processing and 2DEG layer damage within the region of the wafer comprising the 2DEG layer being exploited. The inventors have established a methodology exploiting a first substrate, e.g. silicon, upon which the required lithography processing etc are performed which is then connected to a second substrate, supporting a semiconductor structure providing a 2DEG under defined operating conditions. This connection being achieved through bringing the surface of the second substrate with the 2DEG layer into contact with the surface of the first substrate supporting metallization to apply the electric field to the 2DEG layer. Advantageously this offers the advantage that no processing at all is performed on the 2DEG wafer, offering possibilities for much higher-quality high-mobility devices. Furthermore, the same sets of “gates”, or same device, can sequentially be used on distinct high-mobility wafers. Accordingly, rather than throwing away expensive high-quality wafers, the design methodology of the inventors requires patterning of lower cost wafers, such as silicon, which are also easier to control in terms of manufacturing by exploiting standard high volume semiconductor manufacturing techniques. For example, the technique can be used to provide a low-noise high-frequency pre-amplifier HEMT, which is found in essentially every portable electronic device supporting wireless communications without requiring a discrete amplifier die in conjunction with a silicon integrated circuit.
To the best knowledge of the inventors there has been no technique reported within the prior art fabricating gated electronic devices entirely free of lithography and processing on a two-dimensional electron gas (2DEG) wafer. The technique of the inventors allows silicon substrates, silicon CMOS electronics, and other associated low cost high volume manufacturing rather than custom-grown molecular beam epitaxy (MBE) material that is extremely expensive to grow. Beneficially, the technique also allows for device designs and geometries to be tested on a distinct 2DEG wafer since the devices can be removed from the 2DEG wafer, and replaced with another one. Conversely, several 2DEG materials with different specifications can be tested on a given device design and geometry allowing for rapid prototyping and development. Beneficially the technique is fully compatible with modern high volume foundries. Potentially the technique also allows for low cost integration methodologies for 1D and “zero” D electron gas structures.
According to extensions of the technique two or more different semiconductor materials or material systems may be employed in conjunction with one or more electronic circuits to provide 2DEG enabled circuits in 2D and/or 3D stacked configurations. Further semiconductor materials providing EG elements may incorporate one or more of 2DEG, 1DEG, and “zero” DEG structures.
Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.